1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and particularly a nonvolatile semiconductor memory device of a flash type.
2. Description of the Background Art
A nonvolatile semiconductor memory device of a flash type, i.e., a flash memory is functionally a nonvolatile semiconductor memory device of an entire memory block erasing type allowing electrical programming and erasing. Since such nonvolatile semiconductor memory devices are inexpensive and electrically erasable, they are in great demand for use in portable devices and others, and the research and development of them have been increasingly done in recent years. The flash memory uses transistors (which will be referred to as xe2x80x9cmemory transistorsxe2x80x9d hereinafter) as memory cells. These transistors include floating gates, and have variable threshold voltages, respectively.
The flash memory of the NOR type utilizes hot channel electrons for writing or programming, and therefore can achieve a high write speed.
The NOR type flash memory performs the erasing by changing the threshold voltage of memory transistor from a high to a low.
At present, a flash memory of a type, in which electrons in the floating gate are extracted through an edge into a source region in the erase operation, is the mainstream in the NOR type flash memories. In this invention, description will be made by way of example on applied voltages in the NOR type flash memory, in which electrons are extracted through a whole channel surface for performing the erasing. The NOR type flash memory, in which the erasing is performed by extracting electrons through the whole channel surface, allows scale-down of the cell sizes in contrast to the flash memory of the conventional edge extracting type.
FIG. 21 is a flowchart showing an example of the most simple erase sequence of the conventional flash memory.
Referring to FIG. 21, after an erase command is input in step S101, an erase pulse having a predetermined pulse strength is applied to a memory transistor in subsequent step S102.
Then, determination by an erase verify function is performed in step S103 for determining whether erasing is completed or not.
When it is determined in step S103 that information held in the memory cell is not erased, the processing returns to step S102, and steps S102 and S103 will be repeated until the threshold voltage of memory transistor decreases to or below an erase determination voltage so that the application of the erase pulse and the erase verify are repeated.
When it is determined in step S103 that the threshold voltage of memory transistor is equal to or lower than the erase determination voltage, the processing advances to step S104, and the erasing operation ends.
FIG. 22 is a circuit diagram of a memory block for showing voltages, which are applied during application of the erase pulse in step S102 shown in FIG. 21.
Referring to FIG. 22, this memory block includes memory transistors; which are arranged in n rows and m columns, and each has a floating gate. For applying the erase pulse, a source line potential VSL and a well potential Vwell are both set to 8 V. All word lines for activating the memory transistors in the respective rows are set to xe2x88x9210 V. All bit lines BL1-BLm for reading data from the memory transistors in the respective columns are set to an open state.
FIG. 23 shows voltages applied to the memory transistor when the erase pulse is applied.
Referring to FIG. 23, source line potential VSL applied to a source of the memory transistor and well potential Vwell applied to a substrate of the memory transistor are both set to 8 V. A word line potential VWL applied to the word line for selecting the memory transistor is set to xe2x88x9210 V. In this state, a drain of the memory transistor is in the open state. Since a high electric field is applied not only between the gate and the source but also between the gate and the substrate, erasing is performed by extracting electrons through the whole channel surface of the memory transistor.
FIG. 24 is a circuit diagram showing voltages which are applied for erase verify performed in step S103 of the sequence shown in FIG. 21.
Referring to FIG. 24, well potential Vwell and source line potential VSL are both set to 0 V. Word line WLi which selects the memory transistor corresponding to the selected bit is set to 3.5 V, and the other word lines are all set to 0 V. Bit line BLj connected to the memory transistor corresponding to the selected bit is set to 1.0 V, and the other bit lines are all set to 0 V. The potentials are set as described above, and a current flowing through the memory transistor is determined, whereby it is determined whether erasing of memory transistor MT(i, j) is completed or not.
FIG. 25 shows voltages applied to the memory transistor corresponding to the selected bit in FIG. 24.
Referring to FIG. 25, both the source and well of selected memory transistor MT(i, j) are set to 0 V. The memory transistor receives 3.5 V on its gate, and also receives 1.0 V on its drain.
Description will now be made on voltage setting in the read operation of the conventional flash memory.
FIG. 26 is a circuit diagram showing the voltage setting in the read operation of the conventional flash memory.
Referring to FIG. 26, word line WLi which is connected to the gate of the memory transistor corresponding to the selected bit is set to 4.5 V, and the other word lines are all set to 0 V. In this state, source line potential VSL and well potential Vwell are both set to 0 V.
FIG. 27 shows potentials applied to the memory transistor which is selected in the read operation shown in FIG. 26.
Referring to FIG. 27, both the source and well of the memory transistor corresponding to the selected bit are set to 0 V. The drain carries 1.0 V, and the gate carries 4.5 V. In this state, when the threshold voltage of memory transistor is high, a current does not flow from the drain to the source. When the threshold voltage of memory transistor is low, a current flows from the drain to the source. By detecting this current, it can be determined whether data is already programmed into the memory transistor or not.
When an erase sequence of the conventional flash memory shown in FIG. 21 is used, such a problem may arise that a part of the memory transistors are over-erased. The over-erased state will now be described.
FIG. 28 shows a distribution of the threshold voltages before application of the erase pulse.
Referring to FIG. 28, a programmed state where the memory transistor has stored xe2x80x9c0xe2x80x9d and an erased state where the memory transistor has stored xe2x80x9c1xe2x80x9d are present in the initial state of the erasing operation, i.e., before the erase command is applied in step S101 in FIG. 21. The ordinate in FIG. 28 gives the number of memory transistors holding the respective threshold voltages in the memory block.
In the NOR type flash memory, the state where the threshold voltage is high corresponds to the programmed state, i.e., the state where xe2x80x9c0xe2x80x9d is held. The state where the threshold voltage is low corresponds to the erased state, i.e., the state where xe2x80x9c1xe2x80x9d is held.
In the state shown in FIG. 28, the memory block has already stored data through the preceding sequence, and the numbers of memory transistors in the programmed state and the erased state depend on this stored state, respectively. The memory transistors in the programmed state have the threshold voltages distributed in the range not lower than 5.5 V, and the memory transistors in the erased state have the threshold voltages distributed in a range not exceeding 3.5 V.
FIG. 29 shows an incompletely erased state where the data in all the bits are not completely erased even after the erase pulse was applied in the erase sequence shown in FIG. 21.
Referring to FIGS. 21 and 29, the erase pulse of a predetermined width is applied collectively to all the memory transistors in the memory block in step S102. Thereby, erasing is collectively performed on a memory block by memory block basis by an FN (Fowler-Nordheim) tunnel current. Therefore, when the block containing the memory transistors in the erased state as well as the memory transistors in the programmed state as shown in FIG. 28 is collectively supplied with the erase pulse, the memory cells in the erased state as well as the memory cells in the programmed state shift toward the side, on which the memory cells carry lower threshold voltages in FIG. 28.
FIG. 30 shows a distribution of the threshold voltages in the case where the erase verify is completed in step S103 shown in FIG. 21.
Referring to FIG. 30, after the erase verify is completed, all the memory transistors in the memory block have the threshold voltages no equal to 3.5 V or less. However, it can be seen that the threshold voltages of the respective memory transistors in the memory block are distributed over a considerably wide range. Thus, the threshold voltages in FIG. 30 unpreferably exhibit a large distribution width.
As a result, the memory cells having a threshold voltage of 1 V or less, i.e., the memory cell in the over-erased state are present, as represented by a hatched portion. In the over-erased state, the memory transistor may form a transistor of a depression type in which a drain current flows even when a gate voltage is 0 V.
The foregoing wide distribution is due to variations in threshold voltage of the memory transistors in the erased state as well as variations in threshold voltage of the memory transistors in the programmed state shown in FIG. 28. These variations are further increased by applying the same erase pulse to the memory transistors in the erased state and the memory transistors in the programmed state.
FIG. 31 shows characteristics of the gate voltage and the drain current of the memory transistors having respective threshold voltages in the erased state.
Referring to FIG. 31, when the threshold voltage is 1.5 V or 3.5 V, and gate voltage Vg is 0 V, the drain current is smaller than a determination value. When the threshold voltage is 0 V, however, a current equal to the predetermined determination value flows through the memory transistor even when gate voltage Vg is equal to 0 V. Further, in the memory transistor having the threshold voltage of xe2x88x921.0 V, the drain current disadvantageously flows unless the gate voltage is set to a considerably negative potential.
From comparison between the over-erased memory transistors and the normally erased memory transistors, it can be seen that a large leak current flows even when the over-erased memory transistor forms the depression transistor, and has the gate voltage of 0 V, i.e., when the memory transistor is in the unselected state.
When the above over-erased memory transistor is present, a large leak current flows on the same bit line due to the memory transistor in the unselected and over-erased state when the verify and read are performed with the voltages shown in FIGS. 25 and 27. As a result, the current value of the selected memory transistor cannot be determined due to a sum total of the above leak current. Thus, it is impossible to read out data. Consequently, accurate verify and read are impossible.
FIG. 32 is a flowchart showing a flow employing countermeasures against the problem of over-erasing in the erase sequence shown in FIG. 21.
Referring to FIG. 32, when the erase command is applied in step S111, the erase pulse is collectively applied to the entire memory block in step S112 so that the FN tunnel current changes the threshold voltage. Then, erase verify is executed in step S113. Steps S113 and S112 are repeated until the erased state is detected in all the memory cells. When the erased state is detected in all the memory cells in step S113, the processing advances to step S114.
In step S114, over-erase verify is performed for verifying whether the memory transistor is over-erased or not. More specifically, processing is performed to detect the memory transistor, of which threshold voltage takes a certain value (e.g., 1.5 V) or less after the erase verify is completed. When the over-erased memory transistor is detected, the processing advances to step S115, and over-erase recovery is performed bit by bit. The over-erase recovery is a function of recovering the data bit by bit with channel hot electrons (CHE), and therefore a function of positively increasing the threshold voltage in each memory transistor. The processing advances to step S116, in which it is determined whether the memory transistor in the over-erased state is present or not.
When it is verified that the over-erased memory transistor is not present, the processing advances to step S117. In step S117, the over-recovery verify is performed again because there is a possibility that the over-erase recovery function performed in step S115 caused over-recovery. When the over-recovery is detected, the processing advances to step S112 again. If the memory transistor in the excessively recovered state is not present, the processing advances to step S118, and the erasing ends.
FIG. 33 is a circuit diagram showing voltages which are applied to the memory block during the over-erase verify executed in step S114 shown in FIG. 32.
Referring to FIG. 33, word line WLi for selecting the memory transistor corresponding to the selected bit is supplied with 1.5 V in the over-erase verify operation. The other word lines are supplied with 0 V. A bit line BLj connected to the drain of the memory transistor corresponding to the selected bit is supplied with 1.0 V, and the other bit lines are supplied with 0 V. Source line potential VSL and well potential Vwell are already set to 0 V.
FIG. 34 shows voltages which are applied to the memory transistor corresponding to the selected bit in the over-erase verify operation.
Referring to FIG. 34, the memory transistor of the selected bit receives 0 V on its source and substrate. Also, it receives 1.5 V on its gate, and receives 1.0 V on its drain.
In this manner, a voltage slightly lower than that in the read operation is applied to the gate, and it is determined whether a current flows between the source and drain or not. Thereby, the memory transistor in the over-erased state can be detected.
FIG. 35 is a circuit diagram showing voltages which are applied to the memory block during the over-erase recovery performed bit by bit in step S115 shown in FIG. 32.
Referring to FIG. 35, in the operation of bit by bit over-erase recovery, 7 V is applied to word line WLi selecting the memory transistor corresponding to the selected bit, and the other word lines are supplied with 0 V. Bit line BLj connected to the drain of the memory transistor corresponding to the selected bit is supplied with 4 V. The other bits are supplied with 0 V. Source line potential VSL and well potential Vwell are both set to 0 V.
By setting the gate voltage to a value higher than that (e.g., 4.5 V) in the normal read operation, the drain current flows even through the memory transistor having the threshold voltage in the normal, i.e., xe2x80x9c0xe2x80x9d state. The above voltage may be applied to the memory transistor corresponding to the selected bit, and it may be detected that the current does not flow, whereby the memory transistor in the over-erased state can be detected.
In the case of the erase sequence shown in FIG. 32, recovery is effected on the over-erased memory transistor so that the verify and read can be performed accurately. However, a time is required for the over-erase recovery operation performed bit by bit and the verification thereof. This results in disadvantageous increase in total erase time.
FIG. 36 is a flowchart showing the erase sequence for further reducing the erase time of the erase sequence in FIG. 32.
Referring to FIG. 36, when the erase command is applied in step S111, the processing advances to step S121, and bit by bit program before erasure, i.e., an operation of biasing on a bit by bit basis is performed using channel hot electrons. This bit by bit program before erasure is performed for the purpose of initially setting the erased bits shown in FIG. 28 to the programmed state, and thereby uniformizing the threshold voltages before application of the erase pulse. For changing and uniformizing the threshold voltages, channel hot electrons are used. This narrows the distribution width of the threshold voltages after completion of the erase verify, and therefore reduces the number of the memory transistors to be subjected to the over-erase recovery.
Accordingly, the total erase time can be short. Steps S112-S118 are similar to those shown in FIG. 32, and therefore description thereof is not repeated.
However, even in the case of the erase sequence in which bit by bit program before erasure is performed as shown in FIG. 36, the bit by bit program before erasure requires a long time, resulting in a problem that the total erase time cannot be reduced sufficiently.
FIG. 37 is a flowchart for further reducing the erase time of the erase sequence shown in FIG. 36.
Referring to FIG. 37, this erase sequence includes step S131 instead of step S121 in the flowchart shown in FIG. 36. Instep S131, block program before erasure is collectively executed on a memory block by memory block basis before application of the erase pulse.
According to this manner, the bit by bit programming shown in FIG. 36 is not performed so that the erase time can be reduced.
FIG. 38 is a circuit diagram showing voltages which are applied to the memory block for performing block program before erasure in step S131 shown in FIG. 37.
Referring to FIG. 38, source line potential VSL and well potential Vwell are both set to xe2x88x928 V. All word lines WL1-WLn are set to +10 V. Further, all bit lines BL1-BLm are set to the open state.
FIG. 39 shows voltages applied to the memory transistor for block program before erasure shown in FIG. 38.
Referring to FIG. 39, the source and well of the memory transistor are supplied with xe2x88x928 V, and the gate thereof is supplied with +10 V. The drain is set to the open state. According to this setting, a high electric field is applied between the channel portion and gate of the transistor so that electrons are implanted from the channel portion into the floating gate, and the threshold voltage increases. Thereby, programming is entirely effected on the memory transistors in the memory block.
FIG. 40 shows a distribution of the threshold voltages before the block program before erasure in step S131 of the erase sequence shown in FIG. 37.
Referring to FIG. 40, the memory transistors storing xe2x80x9c1xe2x80x9d have the threshold voltages of 3.5 V or less. The memory transistors storing xe2x80x9c0xe2x80x9d have the threshold voltages which are distributed in a range between 5.5 V and 7 V.
FIG. 41 shows a distribution of the threshold voltages of the memory transistors during the block program before erasure.
Referring to FIG. 41, when the block program before erasure is performed, the threshold voltages of the memory transistors holding xe2x80x9c1xe2x80x9d shown in FIG. 40 and the threshold voltages of the memory transistors holding xe2x80x9c0xe2x80x9d are shifted to a larger side.
FIG. 42 shows a distribution of the threshold voltages exhibited after completion of the block program before erasure.
Referring to FIG. 42, when the threshold voltages of all the memory transistors are 5.5 V or more, the transistors having the threshold voltages increased to about 9 V are present due to variations in threshold voltage. The memory transistors having the increased threshold voltages deteriorate the reliability because an extremely high electric field is applied to tunnel oxide films of the memory cells.
An object of the invention is to provide a nonvolatile semiconductor memory device, which can reduce a total erase time, and can ensure high reliability.
In summary, the invention provides a nonvolatile semiconductor memory device including a memory block, a plurality of word lines, a plurality of bit lines, a potential generating portion and a program/erase control portion.
The memory block includes a plurality of nonvolatile memory transistors arranged in rows and columns. The plurality of word lines select the rows of the memory transistors, respectively. The plurality of bit lines are provided corresponding to the columns of the memory transistors. The potential generating portion generates potentials to be applied to the plurality of word lines, the plurality of bit lines, and substrates and sources of the plurality of memory transistors. The program/erase control portion controls the potential generating portion to erase data in the memory block.
The program/erase control portion includes a first setting portion, a second setting portion and a recovery control portion. The first setting portion collectively and repetitively applies a first erase pulse to the plurality of memory transistors to set the plurality of memory transistors to a first erased state. The second setting portion sets the plurality of memory transistors to a second erased state providing the over-erased memory transistors smaller in number than the over-erased memory transistors in the first erased state. The recovery control portion selectively performs the recovery on the over-erased memory transistors when the second erased state is verified.
Each memory transistor is an MOS transistor having a floating gate. The first erased state is the state, in which the plurality of memory transistors have the threshold voltages equal to or smaller than a first value. The second erased state is the state, in which the plurality of memory transistors have the threshold voltages equal to or smaller than a second value.
According to another aspect of the invention, a method of erasing data of a nonvolatile semiconductor memory device provided with a memory block including a plurality of nonvolatile memory transistors arranged in rows and columns, a plurality of word lines for selecting the rows of the memory transistors, respectively, a plurality of bit lines provided corresponding to the columns of the memory transistors, a potential generating portion for generating potentials to be applied to the plurality of word lines, the plurality of bit lines, and substrates and sources of the plurality of memory transistors, and a program/erase control portion for controlling the potential generating portion to erase data in the memory block, includes the steps of collectively and repetitively applying a first erase pulse to the plurality of memory transistors to set the plurality of memory transistors to a first erased state; setting the plurality of memory transistors to a second erased state providing the over-erased memory transistors smaller in number than the over-erased memory transistors in the first erased state; and performing selectively the recovery on the over-erased memory transistors when the second erased state is verified.
Each memory transistor is an MOS transistor having a floating gate. The first erased state is the state, in which the plurality of memory transistors have the threshold voltages equal to or smaller than a first value. The second erased state is the state, in which the plurality of memory transistors have the threshold voltages equal to or smaller than a second value.
According to the invention, an erase verify voltage for the second erasing is set larger than the erase verify voltage for the first erasing so that the times of application of the erase pulse can be small in number, and therefore a data erasing time of the memory block can be reduced.